Job Description

Job Responsibilities:

• • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• • Power analysis based on netlist

Skills:

• Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
• Experience in chip power analysis
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
• Experience with Python, TCL, Perl programming

Education/Experience:

• Bachelor degree in Electrical/Computer Engineering or Computer Science
• Nice to Have:    MSEE/CS or equivalent experience

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