Description
Provides services in transforming the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power, area and design rules, and optimizing the layout for performance, quality, and reliability, especially in the latest nodes such as 5nm and 3nm.
RTL to GDSII:
Synthesis, Placement and Routing using Fusion Compiler
Block and SOC Floor planning using Fusion Compiler
Clock Tree Synthesis
Signoff checks:
Timing using Primetime
Extraction using Star RC
EMIR closure using Redhawk-SC
ECO implementation:
Logical ECOs using Formality ECO
Timing ECOs using Prime Closure
Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred.
Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization.
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